1. Field of the Invention
The present invention relates to an array substrate and a method of fabricating an array substrate, and more particularly, to a thin film transistor (TFT) array substrate and a method of fabricating a TFT array substrate.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device produces an image by adjusting light transmittance of a liquid crystal material using an electric field. The LCD device includes an LCD panel in which liquid crystal cells are arranged in a matrix configuration, and a driving circuit for driving the LCD panel.
The LCD panel includes a TFT array substrate and a color filter (CF) array substrate that face each other, wherein a spacer is located for maintaining a uniform cell gap between the TFT and CF array substrates and a liquid crystal material is provided within the cell gap.
The TFT array substrate includes gate lines and data lines, a TFT formed as a switching device at each intersection of the gate and data lines, a pixel electrode connected to the TFT formed for each of a plurality of liquid crystal cells, and an alignment film applied to each of the liquid crystal cells. The gate lines and the data lines receive signals from the driving circuits through corresponding pad portions. Accordingly, the TFT, in response to a scan signal supplied to a gate line, supplies a pixel voltage signal transmitted along a data line to the pixel electrode.
The CF array substrate includes a color filter formed by the liquid crystal cell, a black matrix that reflects external light and separates each of the color filters, a common electrode commonly supplying a reference voltage to the liquid crystal cells, and an alignment film disposed on each of the liquid crystal cells.
The LCD panel is fabricated by combining the TFT array substrate and the CF array substrate that have been separately manufactured, injecting the liquid crystal material between the TFT and CF array substrates and sealing the TFT and CF array substrates together with the liquid crystal material therebetween.
In the LCD device, since fabrication of the TFT array substrate involves semiconductor processing including a plurality of individual mask processes, the fabrication process for the TFT array substrate is complicated and is a major cost factor in the fabrication costs of the LCD panel. Thus, fabrication of the TFT array substrate has been developed in order to reduce the number of individual mask processes. For example, one mask process includes multiple individual processes, such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, and inspection processes. Presently, four-round mask processes have been developed, wherein one mask process is reduced from an existing five-round mask process that is employed as a standard mask process.
FIG. 1 is a plan view of a TFT array substrate according to the related art, and FIG. 2 is a cross sectional view along 1-I′ of FIG. 1 according to the related art. In FIGS. 1 and 2, a TFT array substrate includes gate lines 2 and data lines 4 crossing each other and having a gate insulating film 44 therebetween on a lower substrate 42, a TFT 6 formed at each crossing of the gate and data lines 2 and 4, and a pixel electrode 18 formed in a cell region arranged by the crossing of the gate and data lines 2 and 4. In addition, the TFT array substrate includes a storage capacitor 20 formed at an overlapped part of the pixel electrode 18 and a pre-stage gate line 2, a gate pad part 26 connected to the gate line 2, and a data pad part 34 connected to the data line 4.
The TFT 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to a pixel electrode 18, and an active layer 14 of semiconductor pattern 47 defining a channel between the source electrode 10 and the drain electrode 12 and overlapping the gate electrode 8. The active layer 14 overlaps a lower data pad electrode 36, a storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and includes a channel portion defined between the source electrode 10 and the drain electrode 12. In addition, an ohmic contact layer 48 of the semiconductor pattern 47 is used for making an ohmic contact with the lower data pad electrode 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and is further formed on the active layer 14. The TFT 6, in response to the gate signal supplied to the gate line 2, causes a pixel voltage signal supplied to the data line 4 to be charged to and maintained in the pixel electrode 18.
In FIG. 2, the pixel electrode 18 is connected to the drain electrode 12 of the TFT 6 via a first contact hole 16 passing through a passivation film 50. The pixel electrode 18 generates a potential difference along with the common electrode formed on an upper substrate (not shown) by a charged pixel voltage. Due to the potential difference, the liquid crystal material located between the TFT substrate and the upper substrate (not shown) rotates due to a dielectric anisotropy of the liquid crystal material, and transmits incident light through the pixel electrode 18 from a light source (not shown) onto the upper substrate (not shown).
The storage capacitor 20 includes a pre-stage gate line 2, a storage electrode 22 overlapping the pre-stage gate line 2 with the gate insulating film 44, with the active layer 14 and the ohmic contact layer 48 therebetween, and the pixel electrode 18 connected through a second contact hole 24 formed at the passivation film 50 and overlapped with the storage electrode 22 having the passivation film 50 therebetween. The storage capacitor 20 stably maintains the pixel voltage charged to the pixel electrode 18 until a subsequent pixel voltage is charged.
The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad part 26 includes a lower gate pad electrode 28 extending from the gate line 2, and an upper gate pad electrode 32 connected to the lower gate pad electrode 28 via a third contact hole 30 passing through both of the gate insulating film 44 and the passivation film 50. The data line 4 is connected to a data driver (not shown) through the data pad part 34. The data pad part 34 includes the lower data pad electrode 36 extending from the data line 4, and an upper data pad electrode 40 connected to the lower data pad electrode 36 via a fourth contact hole 38 passing through the passivation film 50.
The TFT substrate having the above-described configuration is formed using a four-round mask process.
FIGS. 3A to 3D are cross sectional views along I-I′ of FIG. 1 showing a method of fabricating the TFT array substrate of FIG. 2 according to the related art. In FIG. 3A, gate patterns are formed on the lower substrate 42. On the lower substrate 42, a gate metal layer is formed by a deposition method, such as a sputtering. Subsequently, the gate metal layer is then patterned by photolithography using a first mask and an etching process to form the gate patterns including the gate line 2, the gate electrode 8, and the lower gate pad electrode 28. A material for the gate metal layer includes chromium (Cr), molybdenum (Mo), aluminium (Al) and the like, which are used in a form of a single-layer structure or a double-layer structure.
In FIG. 3B, the gate insulating film 44, the active layer 14, the ohmic contact layer 48, and source/drain patterns are sequentially formed on the lower substrate 42 provided with the gate pattern. The gate insulating film 44, an amorphous silicon layer, an n+ amorphous silicon layer, and a source/drain metal layer are sequentially formed on the lower substrate 42 having the gate patterns thereon by a deposition technique, such as plasma enhanced chemical vapor deposition (PECVD) and sputtering.
For example, a photo-resist pattern is formed on the source/drain metal layer by a photolithography process using a second mask. The second mask employs a diffractive exposure mask having a diffractive exposing part, wherein the diffractive exposing part corresponds to a channel portion of the TFT. As a result, a photo-resist pattern of the channel portion has a lower height than a photo-resist pattern of the source/drain pattern part.
Subsequently, the source/drain metal layer is then patterned by a wet etching process using the photo-resist pattern to form source/drain patterns including the data line 4, the source electrode 10, the drain electrode 12, which is integral to the source electrode 10, and the storage electrode 22.
Next, the amorphous silicon layer and the n+ amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to form the semiconductor pattern 47 including the ohmic contact layer 48 and the active layer 14.
The photo-resist pattern having a relatively low height in the channel portion is removed by an ashing process, and the source/drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 from the drain electrode 12. Then, a remainder of the photo-resist pattern left on the source/drain pattern is removed using a stripping process.
The gate insulating film 44 is made of an inorganic insulating material, such as silicon oxide (SiOx or silicon nitride (SiNx). A metal for the source/drain pattern includes molybdenum (Mo), titanium (Ti), tantalum (Ta), and Mo alloy or the like.
In FIG. 3C, the passivation film 50 including first, second, third, and fourth contact holes 16, 24, 30, and 38 are formed on the gate insulating film 44 having the source/drain patterns. The passivation film 50 is entirely formed on the gate insulating film 44 having the source/drain patterns by a deposition technique, such as a PECVD. Then, the passivation film 50 is patterned by photolithography using a third mask and an etching process to form the first, second, third, and fourth contact holes 16, 24, 30, and 38. The first contact hole 16 is formed to pass through the passivation film 50 and expose the drain electrode 12, whereas the second contact hole 24 is formed to pass through the passivation film 50 and expose the storage electrode 22. The third contact hole 30 is formed to pass through the passivation film 50 and the gate insulating film 44 and expose the lower gate pad electrode 28. The fourth contact hole 38 is formed to pass through the passivation film 50 and expose the lower data pad electrode 36.
The passivation film 50 is made of an inorganic insulating material, such as a material of the gate insulating film 44 or of an organic insulating material having a small dielectric constant, such as an acrylic organic compound, benzocyclobutene (BCB), or perfluorocyclobutane (PFCB).
In FIG. 3D, transparent electrode patterns are formed on the passivation film 50. For example, a transparent electrode material is entirely deposited on the passivation film 50 by a deposition technique, such as a sputtering and the like. Then, the transparent electrode material is patterned by photolithography using a fourth mask and an etching process to provide the transparent electrode patterns including the pixel electrode 18, the upper gate pad electrode 32, and the upper data pad electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the storage electrode 22 overlapping a pre-stage gate line 2. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. Accordingly, the transparent electrode material is made of an indium-tin-oxide (ITO), tin-oxide (TO), or an indium-zinc-oxide (IZO).
As described above, the TFT array substrate and the method of fabricating the TFT array substrate uses a four-round mask process, thereby reducing the number of fabrication processes in comparison with the five-round mask process and reducing fabrication costs. However, since the four-round mask process has a relatively complex fabrication process and reduction of the manufacturing costs is limited, further simplification of the fabrication process and further reduction of the manufacturing costs is required.